Due to the high integration of semiconductor devices, very small wiring is required. Such small wiring causes an increase in the resistance of the wiring and an increase in the signal transfer delay. To solve the problem of signal transfer delay, a multi-layered wiring structure has been introduced for use instead of the prior single layered wiring structure. In the multi-layered wiring structure, the space between wires is further narrowed. As a result, parasitic capacitance between wires on the same layer is increased and the signal transfer delay is worsened. Particularly, in the case of small line width wiring, the signal transfer delay caused by the parasitic capacitance between wires has a marked effect on an operational feature of the semiconductor device.
To reduce parasitic capacitance between wires, it is preferable to reduce the thickness of the wires and to thicken an insulating layer. Accordingly, copper having low resistivity is often used as a wiring material and various materials having low permittivity have been proposed as the insulating layer. However, it is difficult to perform a dry etching when copper is used, since the vapor pressure of etching by-products is low. Therefore, a Damascene process which forms copper wiring by forming a hole (e.g., a via hole or a contact hole) in an insulating layer, filling the hole with copper and planarizing the copper has been used recently.
For the Damascene process, an etch stopper layer is required to perform a chemical mechanical polishing (CMP) process for planarizing copper. If the permittivity of the etch stopper layer is high, the permittivity of the insulating layer is also increased. Thus, the etch stopper layer should be formed of thin material with low permittivity. A representative layer that is currently commonly used as an etch stopper layer is a silicon nitride layer. However, in the CMP process, when adapting an End Point Detection (EPD) system employing an Optical Emission Spectroscopy (OES) method, the etch stopper layer may be easily etched, since the end point of the etching of the wiring material is detected after the silicon nitride layer, (i.e., the etch stopper layer), has already been exposed. Due to this, if the thickness of the etch stopper layer is thin, the etch stopper layer may be easily broken. Thus, it is preferable to use an EPD system employing laser interferometers. This is because loss of the etch stopper layer can be reduced by terminating the etching of wiring material before the exposure of the etch stopper layer. Thus, since it is possible to use a thin etch stopper layer, the permittivity of the whole insulating layer, including the etch stopper layer, may be reduced.
In a conventional metallization process using a Dual Damascene process as shown in FIG. 1, an insulating layer 11 is deposited on a semiconductor substrate 10, (e.g., a single crystal silicon substrate). A contact hole 12 is formed in a part of the insulating layer 11 to expose a contact region (not shown) of the semiconductor substrate 10. A copper barrier layer 13 is formed on an inner wall of the contact hole 12, the surface of the contact region, and the insulating layer 11. A copper layer 15 for filling the contact hole 12 is deposited on the copper barrier layer 13. The copper layer 15 of the contact hole 12 is planarized with the insulating layer 11 by a CMP process. Then, a copper barrier layer 17 such as a nitride layer is deposited on the insulating layer 11 and the copper layer 15. An upper insulating layer 19 is deposited on the copper barrier layer 17. An upper contact hole 20 for exposing a contact region of the copper layer 15 is formed in a part of the upper insulating layer 19.
As shown in FIG. 2, before deposition of the copper barrier layer (e.g., Ta or TaN) in the upper contact hole 20, a copper oxide layer (for example, a CuO layer 16), an insulating layer of a surface of the copper layer, is removed by plasma processing using H2. The CuO layer 16 is parasitically formed on the surface of the copper layer 15 in the course of a wet-treatment of the copper layer 15 for forming the insulating layer 19. The removing process is performed because a contact characteristic of the copper layer 15 and the upper copper layer is deteriorated when a post process for filling the upper contact hole 20 with an upper copper layer (not shown) is performed while leaving the CuO layer 16 as it is.
However, since the conventional method uses explosive H2 gas when removing the CuO layer 16, it has a problem in that the stability of process for removing CuO layer is hardly secured.
In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted.